In a memory device having a redundancy and repair capability, an inner circuit for column and low addresses includes, in addition to X and Y address lines, one or more address lines in each of the X and Y address directions for the purpose of repair. These additional address lines are used for being replaced with defective address lines through a laser trimming process whereby improving yield of the memory devices.
A semiconductor test system performs various types of operational margin tests such as a supply voltage margin test or an access time test. It is an important test item for counting the number of fail bits of the MUT under these tests. For example, in testing a semiconductor wafer, wafer production steps may vary depending on the number of fail bits. If the number of fail bits is greater than the predetermined amount, it is determined that the device is defective and the production process is terminated since it is not repairable. If the number of fail bits is smaller than the predetermined amount, the device is considered to be repairable. Thus, a fail counter is employed in the test system to count the overall fail bits of the MUT.
FIG. 4 shows a basic configuration of such a memory test system.
During the test, output signals from a plurality of MUTs are compared with expected data from a PDS (programmable data selector) 60 by a DC (digital comparator) 75, and the resultant pass/fail information 77.sub.fail is stored in an AFM (address fail memory) 200 in an FM (fail analysis memory) 90. After the test, the AFM 200 reads out the stored information for carrying out the fail analysis.
In the AFM 200, as shown in FIG. 5, it is structured to have a plurality of channels Q in parallel to count the overall fail bits for corresponding MUTs.
Each AFM 200 includes a controller 210, an address pointer 220, an MUX (multiplexer) 230, an MUX 240, a fail memory 250, and a fail counter 260.
The fail memory 250 has a storage memory having at least the same address capacity as that of the MUT. The fail memory 250 is used, firstly, during the memory test process, to store therein the Pass/Fail data which is resulted from comparing the outputs of the MUT with the expected data by the DC 75. Address signals from a PG (pattern generator) 50 is used as the address information for this process.
Secondly, in the fail analysis process, the data in the fail memory 250 is read out to count the overall number of fail bits. In this situation, by switching the MUX 230, the address information for reading the data in the fail memory 250 is provided from the controller 210 through the address pointer 220. All of the addresses are sequentially generated and the fail bits are counted by the counter 260. In this example, the fail counter 260 is a type of counter which counts up when the fail data is "1".
The controller 210, in receiving fail analysis parameters from a CPU, controls the address generation sequence for counting the number of the fail bits. The address pointer 220 generates address signals to be supplied to the fail memory 250. The address pointer 220 generates the address signal by counting up for a desired bit area in an N bit address signal and provides the generated address signal to the MUX 230.
The MUX 230 is a selector which, in receiving a select signal from the controller 210, outputs the address signals from the PG 50 during the measurement while outputs the address signals from the address pointer 220 during the fail analysis.
The MUX 240 is a selector to select address signals 242.sub.adr to be supplied to the fail memory 250 in a manner that the fail memory 250 has the same address space as that of the MUT. For example, the MUX 240 provides the address signal in which unused upper addresses are set to zero.
The foregoing is the explanation of the basic structure of the AFM 200. The counting operation in the AFM 200 is explained in the following with reference to the drawings.
FIG. 6 shows an example of data stored in the fail memory 250 when the number of address bits of the MUT is eight, and the X and Y addresses are provided to the fail memory 250 in which the X address is 4 bits and the Y address is 4 bits.
In the example of FIG. 6, to count all of the fail data, the address (X, Y) is sequentially incremented from (0, 0) to (F, F) to access all of 256 addresses while counting the number of fail data. In this example, the counted number is "18". Because it is necessary to apply all of the addresses to the fail memory and read the fail data therefrom, it takes a long time for counting the number which is proportional to the capacity of the memory. Thus, it requires a long time for counting the fails in a large scale memory device.
As noted above, to count all of the fail data, it is necessary to apply all of the addresses to the fail memory and read the fail data therefrom for counting up the fail data. Thus, it takes a time for counting the fails in proportion to the capacity of the memory device, which adversely affects a test throughput in the device testing for large capacity memories such as 64M bit or 250M bit memory devices.
Therefore, it is an object of the present invention to provide counting means which is capable of reducing the time for counting the number of fail bits by reading out the data from the fail memory in a plural bit form at the same time and counting the fail bits in parallel at the same time.